EMPLOYMENT HISTORY
Senior Embedded System Engineer
2019
– Current
Continental Electronics Pte Ltd
Development and prototyping of various electronics products. Sky is the limits!
Founder Engineer
2018
– 2019
Alam Pelangi Envirotech
Development and prototyping of IOT product, bridging the analog world to digital computing. Implementing high precision, super speed analog-to-digital module. Negotiate with potential customers, vendors, and managing engineering, marketing and sales team. Response and bid on call-for-tender projects. Seeking and pitching for investors to help accelerate the completion of the project.
Software Engineer
Dec 2018
– Apr 2019
Cell ID Pte Ltd
Development and integration of biomedical electronics system firmware and software by C/C#. Design solution for PCR procedure, enabling and troubleshooting of the electronics system, and recommending hardware optimization of the system.
Lecturer
Sep 2017
– Dec 2018
Southern University College (Johor)
Covered various engineering topics such as Electronics Instrumentation, VLSI system Design, Digital Signal Processing, Signal and Systems, C/C++/C# Programming and Higher Engineering Mathematics. Successfully guided Diploma Students on their final year projects which encompass various engineering problems.
Senior Component Design Engineer
Dec 2016
– July 2017
Usains Infotech Sdn Bhd (Infinec)
Successfully completed the designated CBB layout under a contract with our contract client: Intel Microelectronics. Helped the DDR/MIG MD team during the critical transition period from 14nm technology to 10nm technology.
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Design integrated circuit schematics (ADT DDR) to pass FEV (Formal Equivalence Verification)
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Tape-in schematics to layout. Design and floorplan digital and analogue layout using Genesys (CAD tool) to meet DRC (Design Rule Check), and RV (Reliability Verification) to tape-in for production.
Research Engineer
Jul 2012
– Sep 2015
Hitachi Critical Facilities Protection Pte Ltd
Leads the R&D team to design new product from concept to micro-production of golden sample. The team had successfully improved the performance of HCFP’s core surge protection device and greatly reduce the production costs by re-design the PCB, components and careful selection of new components. She was part of the pioneer R&D team member who successfully set up a high voltage test lab for HCFP. She build up a 10kV 5kA surge generator to perform tests on new products.
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Product design including improvement, new product development of all stages.
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Introduce product concept & solution. Design circuitry, simulation models, build schematics, footprints library, component placement, PCB layout routing, BOM, marketing prototype building, functional prototype building and testing, final production golden sample preparation.
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Design art stages which met DFM, going through TRLA (Technology Readiness Level Assessment) & MRLA (Manufacturing Readiness Level Assessment)
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Working together with procurement to source & negotiates for BOM purchases.
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Plan & perform tests for new products for IEC/UL/JIS standard tests.
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Documentation on product EC self certification.
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Working with marketing to perform public demonstration, expo, shows, & business partner presentation on new products.
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Roadmap & budget planning on new product design.
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Prior art search & evaluating product patentability. Document preparation & log booking for R&D process.
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Develop test methods/technique, integrate and validate test program for surge protection devices and varistor components.
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Customer's site survey to collect realistic data, identify problems and propose new design improvement.
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Meeting with customer to analyze their needs & provide technical support to sales account manager for preparation of quotation for the customers.
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Responsible to set up high voltage test lab. Building of 10kV 5kA surge generator to perform tests on new products.
Component Design Engineer
Jun 2008
– Jun 2012
Intel Microelectronics (M) Sdn Bhd
Successfully completed the designated fub layout for Westmere and Haswell projects on schedule. At the same time, she provided support for her colleagues on their fubs. During the 2nd year of her employment, she expanded her career by taking up schematic design for RF (Register Files) fubs.
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Design integrated circuit schematics (Register Files) to pass FEV (Formal Equivalence Verification), converge timing, power, noise and quality requirements internally and externally to section.
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Re-design and implement new schematic topology to meet timing and power requirement.
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Tape-in schematics to layout. Design digital and analogue layout using Genesys (CAD tool) to meet DRC (Design Rule Check), and RV (Reliability Verification) to tape-in for production.
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4 years Digital Integrated Circuit mask design experience.
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1+ years Analogue Integrated Circuit mask design experience.
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1+ years Digital Integrated Circuit design experience.
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Chartered 28nm layout design to meet DRC & production rules.
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Digital core RF (Register Files) circuit design from RTL to schematics.
INTERNSHIP HISTORY
Intern (FOL Wire Bonding Process)
Jan 2007
- Jun 2007
​UNISEM (M) Sdn. Bhd
Prepare and execute DOE to improve machine performance, yield and wire bonding quality. Study on different wire-bonding methods, materials and mechanism for various types of IC packages. Troubleshoot low yield lot, providing support to technician and operators.
Intern (Patent)
Feb 2016
– Mar 2016
Hiraki & Associates
Short-term fellowship training organized by World Intellectual Property Organization (WIPO) with support of the Japan Patent Office (JPO).